1. Field of the Invention
This invention relates to nonvolatile semiconductor memories, and more particularly to electrically erasable programmable read-only memory devices of large capacity.
2. Description of the Related Art
With the increasing needs for high performance and high reliability of digital computer systems, it is strongly required to develop a rewritable semiconductor memory having a memory capacity which is so large that the memory can be used instead of an existing external data storing medium such as a magnetic disk or a fixed disk unit (which is sometimes called a "hard disk device") used for a computer.
Recently, in order to meet the above requirement, an electrically erasable programmable nonvolatile read-only memory (hereinafter referred to as an "EEPROM" according to the custom of this technical field) in which the memory integration density is enhanced by reducing the number of transistors used in each memory section on a chip substrate with limited size has been proposed and developed.
This type of EEPROM is typically called a "NAND type EEPROM" in which series circuits of floating gate type metal oxide semiconductor field effect transistors (referred to as "MOSFETs" hereinafter) are connected to a corresponding bit line via a switching transistor. The switching transistor is rendered conductive when designated to selectively connect the series array of floating gate type MOSFETs to a corresponding bit line associated therewith, and is generally called a "select transistor."
Each of the serially arrayed floating gate type MOSFETs is a minimum element for storing data and may be considered to correspond to a memory cell of a conventional dynamic random access memories, that is, DRAMs (of course, the series array of MOSFETs itself is sometimes called a "memory cell." The naming is not particularly important. For example, in this patent specification, each series array of MOSFETs will be named as a "NAND cell unit"). In general, each transistor array consists of 4, 8 or 16 floating gate type MOSFETs. Each MOSFET has a control gate connected to a corresponding word line and a floating gate for storing charges representing logic data of "1" or "0." Since each memory cell can be formed of one floating gate type MOSFET, the integration density of the EEPROM can be enhanced and therefore the memory capacity thereof can be increased.
In the above NAND type EEPROM, data is sequentially written into the floating gate type MOSFETs, that is, memory cell transistors in each NAND cell unit. In a case where logic data is written into the EEPROM at a desired memory address, that is, into a selected one of the floating gate type MOSFETs of the designated NAND cell unit, a high voltage Vpp of 20 volts, for example, and an intermediate voltage Vppm--it has a potential level between the power source voltage Vcc of the EEPROM and the high voltage Vpp and is typically set at 10 volts when the power source voltage Vcc is 5 volts--are used as follows. The high voltage Vpp is applied to the control gate electrode of a selected memory cell transistor, and the intermediate voltage Vppm is applied to the control gate electrodes of non-selected memory cell transistors lying between the selected memory cell transistor and the select transistor. The non-selected memory cell transistors are rendered conductive.
When, under this condition, a voltage of 0 volt is applied to a corresponding bit line as a data voltage representing a logic data value, the data voltage is transmitted to a target memory cell, that is, to the drain of the selected floating gate type MOSFET via the non-selected memory cell transistors which are rendered conductive. Therefore, in the MOSFET, electrons are injected by the tunnel effect from the drain into the floating gate electrode thereof. As a result, the threshold value of the MOSFET is shifted in a positive direction. Thus, logic data "1" is stored into a desired address location.
When the intermediate voltage Vppm is applied to the bit line, injection of electrons will not occur in the selected floating gate type MOSFET. In this case, the threshold value of the MOSFET is kept unchanged. This state is defined as a logic "0" storing state.
The operation of erasing data in the NAND cell type EEPROM is simultaneously effected for each predetermined block, which is generally the entire portion of one chip of the EEPROM is dealt as one block. This is so-called "simultaneous erasing." At this time, all of the NAND cell units of the EEPROM are electrically separated from the bit lines, substrate and source voltage. The control gate electrodes of all of the memory cell transistors are set at 0 volt and the substrate voltage (and the well potential if the NAND cell units are formed in a well region) is set to the high voltage Vpp. As a result, in all of the memory cell transistors, electrons are moved from the floating gate electrodes thereof to the substrate (or the well region). The threshold values thereof are shifted in a negative direction. The stored data items are electrically erased at the same time.
In order to selectively read out the stored data of a specified memory cell transistor, 0 volt is applied to the control gate electrode of the selected memory cell transistor. All of the remaining memory cell transistors of the EEPROM are set to the power source voltage Vcc (5 volts) All of the select transistors are rendered conductive by application of the power source voltage Vcc to the gate electrodes thereof. The logic value of the stored data can be determined by checking whether or not current flows in a common source layered line which is also associated with the specified NAND cell unit including the selected memory cell transistor.
In the above data write-in mode, those of the non-selected memory cell transistors of each NAND cell unit which lie between the target memory cell transistor and the select transistor function as "transfer gates" for transferring a logic data voltage to the selected memory cell transistor. It may be considered that the non-selected memory cell transistors also function as transfer gates for transferring readout data in the data readout mode.
In order to keep the data transferring efficiency high, the threshold values thereof are required to be always set within a properly defined range. Further, the EEPROM comes with variation in the power source voltage itself, variation in quality caused in the manufacturing process and/or aging deterioration of the physical property of the EEPROM under various application environments (especially, temperature) for the end users. Taking such fact into consideration, it would be desirable to design a range narrower than the above range so as to add a safety margin. After the simultaneous erasing operation is repeatedly effected in the NAND cell type EEPROM, the threshold values of the memory cell transistors will vary. Actually manufactured NAND cell EEPROMs are required to sufficiently "absorb" such variations in the threshold values. Otherwise, the reliability of the EEPROMs obtained after the shipment from the semiconductor manufacturers cannot be expected to be high.
Conventionally, compensation for variation in the threshold values of memory cell transistors has been made at the LSI design level. For example, floating gate type MOSFETs are so designed that the threshold values thereof may be set within a range of 0.5 to 3.5 volts. In the manufacturing process, actually obtained EEPROMs are individually subjected to the threshold value test. Only those of the EEPROMs which have passed the test are shipped. As an example of such test, the electrical threshold value distribution measurement based on the readout current detection in the manufacturing line, and a threshold value variation test by an aging test under the atmosphere of high temperature are carried out; those of the products which have not passed the tests are rejected. In this way, the operation reliability of the NAND cell type EEPROMs has been enhanced.
However, only with the above measure, it cannot be expected to improve the operation reliability of NAND cell type EEPROMs while the manufacturing yield thereof is kept high. The main reason is as follows: no sorting test is actually effected for spatial or temporal variation in the threshold value caused by simultaneous erasing of data. This is because the control circuit is inevitably made complicated in construction if the above sorting test is effected. The threshold values of the memory cell transistors at the time of data erasing are of the negative polarity. In order to measure the value, it is naturally required to use a negative bias voltage. No negative power source is used in the control circuits contained in ordinary NAND cell type EEPROMs. If a power source of negative polarity is forcedly used in such a construction, an exclusive external connection terminal must be specially added to each package of the EEPROMs. The construction of the control circuit therefor is made complicated. In practice, the above modification made only for the reliability test cannot be satisfactorily accepted by the semiconductor manufacturers who are strictly required to reduce the cost of the products.